1. Field
This disclosure relates generally to data processors, and more specifically, to data processors that execute instructions which create control vectors for supporting circular buffers.
2. Related Art
Increased performance in data processing systems can be achieved by allowing parallel execution of operations on multiple elements of a vector. One type of processor available today is a vector processor which utilizes vector registers for performing vector operations. However, vector processors, while allowing for higher performance, also have increased complexity and cost as compared with processors using scalar general purpose registers. That is, a vector register file within vector processors typically includes N vector registers, where each vector register includes a bank of M registers for holding M elements. Another type of known processor is a single-instruction multiple-data (SIMD) scalar processor (also referred to as a “short-vector machine”) which allows for limited vector processing while using any existing scalar general purpose register (GPR). Therefore, although the number of elements per operation is limited as compared to vector processors, reduced hardware is required.
Many different applications executed on SIMD processors use circular buffers to hold SIMD elements. For example, many types of filtering algorithms in digital signal processing (DSP) applications use circular buffers to hold sets of input samples and computed output samples. However, inefficiencies arise when using circular buffers, since the addressed data elements “wrap” around a particular memory or register boundary. Extracting a set of elements around the “wrap” point into a SIMD register requires overhead to properly handle the wrapping, which results in reduced efficiency.